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M40SZ100Y M40SZ100W
5V or 3V NVRAM SUPERVISOR FOR LPSRAM
FEATURES SUMMARY s CONVERT LOW POWER SRAMs INTO NVRAMs
s s
Figure 1. 16-pin SOIC Package
5V OR 3V OPERATING VOLTAGE PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION WHEN VCC IS OUT-OF-TOLERANCE CHOICE OF SUPPLY VOLTAGES and POWER-FAIL DESELECT VOLTAGES: - M40SZ100Y: VCC = 4.5 to 5.5V; 4.20V VPFD 4.50V - M40SZ100W: VCC = 2.7 to 3.6V; 2.55V VPFD 2.70V RESET OUTPUT (RST) FOR POWER ON RESET 1.25V REFERENCE (for PFI/PFO) LESS THAN 10ns CHIP ENABLE ACCESS PROPAGATION DELAY (at 5V) OPTIONAL PACKAGING INCLUDES A 28LEAD SOIC and SNAPHAT(R) TOP (to be ordered separately) 28-LEAD SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY BATTERY LOW PIN (BL) Figure 2. 28-pin SOIC Package*
SNAPHAT (SH) Battery
16 1
s
SO16 (MQ)
s
s
s s
s
28 1
s
SOH28 (MH)
s
* Contact Local Sales Office
September 2003
Rev. 1.3
1/19
M40SZ100Y, M40SZ100W
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 3.) . . . . . . . Signal Names (Table 1.) . . . . . . . . SOIC16 Connections (Figure 4.) . . SOIC28 Connections (Figure 5.) . . Block Diagram (Figure 6.) . . . . . . . Hardware Hookup (Figure 7.) . . . . ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...........3 ...........3 ...........4 ...........4 ...........4 ...........5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Testing Load Circuit (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Testing Input/Output Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Down Timing (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Up Timing (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-on Reset Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset Input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 RSTIN Timing Waveform (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Battery Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SNAPHAT(R) Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
M40SZ100Y, M40SZ100W
SUMMARY DESCRIPTION The M40SZ100Y/W NVRAM Controller is a selfcontained device which converts a standard lowpower SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the conditioned chip enable output (ECON) is forced inactive to write protect the stored data in the SRAM. During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the SNAPHAT (or external battery for the 16-lead SOIC) to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns. The 28-pin, 330 mil SOIC provides sockets with gold plated contacts for direct connection to a separate SNAPHAT(R) housing containing the battery. The SNAPHAT housing has gold plated pins which mate with the sockets, ensuring reliable connection. The housing is keyed to prevent improper insertion. This unique design allows the SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the surface mount process which greatly reduces the board manufacturing process complexity of either directly soldering or inserting a battery into a soldered holder. Providing non-volatility becomes a "SNAP." This feature is also available in the "topless" 16-pin SOIC package (MQ). Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The 28-pin SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4ZXX-BR00SH" (see Table 13, page 17). Caution: Do not place the SNAPHAT battery top in conductive foam, as this will drain the lithium button-cell battery.
Figure 3. Logic Diagram
VCC VBAT
(1)
Table 1. Signal Names
E ECON RST Chip Enable Input Conditioned Chip Enable Output Reset Output (Open Drain) Reset Input Battery Low Output (Open Drain) Supply Voltage Output Supply Voltage Back-up Supply Voltage Power Fail Input Power Fail Output Ground Not Connected Internally
VOUT E PFI RSTIN M40SZ100Y M40SZ100W BL
RSTIN BL VOUT
ECON PFO
VCC VBAT (1)
RST
PFI PFO
VSS
Note: 1. For 16-pin SOIC package only.
VSS
AI03933
NC
Note: 1. For SO16 only.
3/19
M40SZ100Y, M40SZ100W
Figure 4. SOIC16 Connections Figure 5. SOIC28 Connections
NC NC RST NC RSTIN PFO VBAT VSS
1 16 15 2 14 3 4 M40SZ100Y 13 5 M40SZ100W 12 11 6 7 10 8 9
VCC NC VOUT NC PFI BL E ECON
AI03935
BL NC NC NC NC NC NC NC RSTIN NC NC NC PFO VSS
1 28 27 2 26 3 25 4 24 5 23 6 7 M40SZ100Y 22 8 M40SZ100W 21 20 9 19 10 18 11 17 12 16 13 15 14
AI03934
VCC NC NC VOUT NC NC PFI NC E NC RST NC NC ECON
Note: 1. DU = Do Not Use
Figure 6. Block Diagram
VCC VOUT
VBAT VBL= 2.5V COMPARE BL (1)
VSO = 2.5V
COMPARE
VPFD= 4.4V
COMPARE
POR
(2.65V for SZ100W) RSTIN RST(1)
E PFI COMPARE 1.25V
ECON
PFO
AI04766
Note: Open drain output
4/19
M40SZ100Y, M40SZ100W
Figure 7. Hardware Hookup
3.0V, 3.3V or 5V Regulator Unregulated Voltage VIN VCC VCC VOUT VCC M40SZ100Y M40SZ100W E From Microprocessor RSTIN R1 PFI R2 VSS VBAT(1) RST BL To Microprocessor Reset To Battery Monitor Circuit ECON PFO To Microprocessor NMI 0.1F 1Mb or 4Mb LPSRAM E
0.1F
AI04767
Note: 1. User supplied for the 16-pin package
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TSTG TSLD(1) VIO VCC IO PD Parameter Storage Temperature (VCC Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value SNAPHAT SOIC -40 to 85 -55 to 125 260 -0.3 to VCC +0.3 M40SZ100Y M40SZ100W -0.3 to 7 -0.3 to 4.6 20 1
Unit C C C V V V mA W
Note: 1. Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 to 120 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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M40SZ100Y, M40SZ100W
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 3. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M40SZ100Y 4.5 to 5.5V -40 to 85C 100pF 5ns 0.2 to 0.8VCC 0.3 to 0.7VCC M40SZ100W 2.7 to 3.6V -40 to 85C 50pF 5ns 0.2 to 0.8VCC 0.3 to 0.7VCC
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Figure 8. AC Testing Load Circuit
Figure 9. AC Testing Input/Output Waveforms
DEVICE UNDER TEST
333
0.8VCC CL = 100pF or 50pF 1.73V 0.2VCC
0.7VCC 0.3VCC
AI02568
CL includes JIG capacitance
AI02393
Note: 1. CL = 100pF for M40SZ100Y and 50pF for M40SZ100W.
Table 4. Capacitance
Symbol CIN COUT(3) Input Capacitance Output Capacitance Parameter(1,2) Min Max 7 10 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected
6/19
M40SZ100Y, M40SZ100W
Table 5. DC Characteristics
Sym ICC ICCDR Parameter Supply Current Data Retention Mode Current(2) Input Leakage Current Input Leakage Current (PFI) Output Leakage Current VOUT Current (Active) VOUT Current (Battery Back-up) Battery Voltage Input High Voltage Input Low Voltage Output High Voltage(7) VOH Battery Backup(8) Output Low Voltage VOL Output Low Voltage (open drain)(9) Power-fail Deselect Voltage PFI Input Threshold PFI Hysteresis VSO
Note: 1. 2. 3. 4. 5. 6. 7. 8.
Test Condition(1) Outputs open
M40SZ100Y Min Typ Max 1 50 200 1 -25 2 25 1 175 100 2.5 0.7VCC -0.3 3.0 3.5(6) 2.5 -25 Min
M40SZ100W Typ Max 0.5 50 200 1 2 25 1 100 100 3.0 3.5(6) VCC + 0.3 0.3VCC
Unit mA nA A nA A mA A V V V V
0V VIN VCC
ILI(3)
ILO(4) IOUT1(5) IOUT2 VBAT VIH VIL VOH VOHB
0V VOUT VCC VOUT > VCC - 0.3 VOUT > VBAT - 0.3
VCC + 0.3 0.7VCC 0.3VCC -0.3 2.4 2.9 3.5 0.4 0.4 2.5 2.9
IOH = -1.0mA IOUT2 = -1.0A IOL = 3.0mA IOL = 10mA
2.4 2.5
3.5 0.4 0.4
V V V V V mV V
VPFD
4.20 VCC = 5V(Y) VCC = 3V(V) PFI Rising 1.225
4.40 1.250 20 2.5
4.50 1.275 70
2.55 1.225
2.60 1.250 20 2.5
2.70 1.275 70
VPFI
Battery Back-up Switchover Voltage
Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 3.6V or 4.5 to 5.5V(except where noted). Measured with VOUT and ECON open. RSTIN internally pulled-up to VCC through 100k resistor. Outputs deselected. External SRAM must match SUPERVISOR chip VCC specification (3V or 5V). For rechargeable back-up, VBAT (max) may be considered VCC - 0.5V. For PFO pin (CMOS). Chip Enable output (ECON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will reduce battery life. 9. For RST & BL pins (Open Drain).
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M40SZ100Y, M40SZ100W
OPERATION The M40SZ100Y/W, as shown in Figure 7, page 5, can control one (two, if placed in parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (ECON) output pin follows the chip enable (E) input pin with timing shown in Table 6, page 10. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V (IOUT1). When VCC degrades during a power failure, ECON is forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). For the M40SZ100Y/W the power fail detection value associated with VPFD is shown in Table 5, page 7. If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time tWPT, ECON is unconditionally driven high, write protecting the SRAM. A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user can be assured the memory will be write protected within the Write Protect Time (tWPT) provided the VCC fall time does not exceed tF (see Table 6, page 10). As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO ). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 5, page 7). When VCC rises above VSO, VOUT is switched back to the supply voltage. Output ECON is held inactive for tCER (120ms maximum) after the power
supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 11, page 10). Data Retention Lifetime Calculation Most low power SRAMs on the market today can be used with the M40SZ100Y/W NVRAM Controller. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40SZ100Y/W and SRAMs to be "Don't care" once VCC falls below VPFD(min) (see Figure 10, page 9). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the ICCDR value of the M40SZ100Y/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT(R) of your choice (see Table 13, page 17) can then be divided by this current to determine the amount of data retention available. CAUTION: Take care to avoid inadvertent discharge through VOUT and ECON after battery has been attached. For a further more detailed review of lifetime calculations, please see Application Note AN1012.
8/19
M40SZ100Y, M40SZ100W
Figure 10. Power Down Timing
VCC VPFD (max) VPFD VPFD (min) VSO
tF tFB
E tWPT VOHB ECON
RST
PFO
VALID
AI03936
9/19
M40SZ100Y, M40SZ100W
Figure 11. Power Up Timing
VCC VPFD (max) VPFD VPFD (min) VSO
tR tRB E tEPD ECON VOHB tREC RST tEPD tCER
PFO
VALID
AI03937
Table 6. Power Down/Up AC Characteristics
Symbol tF(2) tFB(3) tPFD tR tEPD tRB tCER tREC tWPT Parameter(1) VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time PFI to PFO Propagation Delay VPFD(min) to VPFD (max) VCC Rise Time Chip Enable Propagation Delay (Low or High) VSS to VPFD (min) VCC Rise Time Chip Enable Recovery VPFD (max) to RST High Write Protect Time M40SZ100Y M40SZ100W 1 40 40 40 120 200 200 Min 300 10 15 10 10 15 25 Max Unit s s s s ns ns s ms ms s
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 3.6V or 4.5 to 5.5V(except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
10/19
M40SZ100Y, M40SZ100W
Power-on Reset Output All microprocessors have a reset input which forces them to a known state when starting. The M40SZ100Y/W has a reset output (RST) pin which is guaranteed to be low by VPFD (see Table 5, page 7). This signal is an open drain configuration. An appropriate pull-up resistor to VCC should be chosen to control the rise time. This signal will be valid for all voltage conditions, even when VCC equals VSS (with valid battery voltage). Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low for tREC to allow the power supply to stabilize. Figure 12. RSTIN Timing Waveform
RSTIN tRLRH RST
(1)
Reset Input (RSTIN) The M40SZ100Y/W provides one independent input which can generate an output reset. The duration and function of this reset is identical to a reset generated by a power cycle. Table 7 and Figure 12 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH will not generate a reset condition. RSTIN is internally pulled up to VCC through a 100k resistor.
tR1HRH
AI04768
Note: With pull-up resistor
Table 7. Reset AC Characteristics
Symbol tRLRH(2) tR1HRH(3) Parameter(1) RSTIN Low to RSTIN High RSTIN High to RST High Min 200 40 200 Max Unit ns ms
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted). 2. Pulse width less than 50ns will result in no RESET (for noise immunity). 3. CL = 5pF (see Figure 8, page 6).
11/19
M40SZ100Y, M40SZ100W
Battery Low Pin The M40SZ100Y/W automatically performs battery voltage monitoring upon power-up, and at factory-programmed time intervals of at least 24 hours. The Battery Low (BL) pin will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL pin will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below 2.5V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The M40SZ100Y/W only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control the rise time. Power-fail Input/Output The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from the VPFD comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an under-voltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 7, page 5) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the M40SZ100Y/W or the microprocessor drops below the minimum operating voltage. During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low. This oc-
curs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI for the write protect time (tREC), which is the time from VPFD (max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 13) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 13. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI00622
12/19
M40SZ100Y, M40SZ100W
PACKAGE MECHANICAL INFORMATION Figure 14. SO16 - 16-lead Plastic Small Package Outline
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Note: Drawing is not to scale.
Table 8. SO16 - 16-lead Plastic Small Plastic Package Mechanical Data
mm Symbol Typ. A A1 A2 B C D E e H L a N CP 1.27 0.35 0.19 9.80 3.80 - 5.80 0.40 0 16 0.10 0.10 Min. Max. 1.75 0.25 1.60 0.46 0.25 10.00 4.00 - 6.20 1.27 8 0.050 0.014 0.007 0.386 0.150 - 0.228 0.016 0 16 0.004 0.004 Typ. Min. Max. 0.069 0.010 0.063 0.018 0.010 0.394 0.158 - 0.244 0.050 8 inches
13/19
M40SZ100Y, M40SZ100W
Figure 15. SOH28 - 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Drawing is not to scale.
Table 9. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
14/19
M40SZ100Y, M40SZ100W
Figure 16. SH - 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note: Drawing is not to scale.
Table 10. SH - 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
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M40SZ100Y, M40SZ100W
Figure 17. SH - 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note: Drawing is not to scale.
Table 11. SH - 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090 inches
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M40SZ100Y, M40SZ100W
PART NUMBERING Table 12. Ordering Information Scheme
Example: M40SZ 100Y MQ 6 TR
Device Type M40SZ
Supply Voltage and Write Protect Voltage 100Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V 100W = VCC = 2.7 to 3.6V; VPFD = 2.6 to 2.7V
Package MQ = SO16 MH(1,2) = SOH28
Temperature Range 6 = -40 to 85C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT (R)) which is ordered separately under the part number "M4ZXX-BR00SHX" in plastic tube or "M4ZXX-BR00SHXTR" in Tape & Reel form. 2. Contact Local Sales Office Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH" in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 13. SNAPHAT(R) Battery Table
Part Number M4Z28-BR00SH M4Z32-BR00SH Description SNAPHAT Housing for 48mAh Battery SNAPHAT Housing for 120mAh Battery Package SH SH
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M40SZ100Y, M40SZ100W
REVISION HISTORY Table 14. Document Revision History
Date December 2001 13-May-02 01-Aug-02 15-Sep-03 Rev. # 1.0 1.1 1.2 1.3 First Issue Modify reflow time and temperature footnote (Table 2) Add marketing status (Figure 2; Table 12) Remove reference to M68xxx (obsolete) part (Figure 7); update disclaimer Revision Details
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M40SZ100Y, M40SZ100W
M40SZ100, M40SZ100Y, M40SZ100W, 40SZ100, 40SZ100Y, 40SZ100W, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, RTC, RTC, RTC, RTC, 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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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